This invention relates to a clock phase control system; and it relates, more particularly, to such a system in which a correction for a phase error specified by a set of digital signals is implemented in steps over a period of time.
In clock phase control systems, the output of a high-frequency oscillator is often counted down by a presettable, i.e., programmable, binary counter to obtain a variety of clock signals of different frequencies and phases. The phase adjustment is typically effected by either an add/delete technique or a technique in which the desired phase of operation of a clock system is first determined by separate logic; and then, the clock count-down circuit is reset, or preset, to some fixed predetermined value, which it is desired to maintain at the correct clock phase time, e.g., a binary signal information transition time. Examples of clock phase control systems of this type are represented by the U.S. Pat. No. 3,668,315 issued to J. O. Heitzman, U.S. Pat. No. 4,216,544 issued to A. Boleda et al., and U.S. Pat. No. 3,697,689 issued to E. D. Gibson.
In the present state of the art, electronic systems are often controlled by microprocessors which perform data processing functions, including arithmetic functions, using the so-called two's-complement arithmetic. Clock systems heretofore available usually operate on a one's-complement basis using both positive and negative zero, and are not directly responsive to two's-complement information values so are not directly usable with microprocessor control.
Oftentimes, an electronic system which is synchronized by a clock operates at a much higher frequency than does a microprocessor which controls that system. Accordingly, a phase error signal provided to the clock by such a microprocessor could well, if it were implemented in a single presetting step (wherein one cycle of the microprocessor could encompass many periods of the controlled clock), have a significant adverse impact on the operation of the controlled electronic system circuits.